Srinivasan Venkataramanan
Summary
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SeniorSrinivasan Venkataramanan is a results-driven technology leader and founder with a global footprint across the UK, US (San Jose), and India, focused on advancing VLSI verification methodologies. He currently serves as CEO of AsFigo and as CEO & Co-Founder of VerifWorks, while guiding technical strategy as CTO of CVC, a role he has held since 2009. A prolific technical evangelist, he has authored and contributed to multiple books on SystemVerilog, PSL/Sugar, and verification methodologies, and engages with the standards community through IEEE and Accellera activities. He has driven cutting-edge verification for multi-million-gate ASICs across design houses and EDA firms, and even led machine learning initiatives within chip design at Synopsys. An active conference contributor and program committee member at DVCon and DAC, he also founded VerifNews to aggregate global design-verification news. Based in London, he combines hands-on engineering depth with strategic leadership, blending industry insight from both the design and EDA sides to shape roadmaps for near-term innovation.
9 years of coding experience
Stackoverflow
11reputation
1kreached
2answers
0questions
Github Skills (96)
verilog10
near10
simulator10
testing10
vhdl10
asic10
cpp10
icarus10
bottom-up10
fpga10
unit-testing-framework10
testbench10
silicon10
systemverilog10
bottom10
Programming languages (9)
Github contributions (5)
AsFigo/pyslint
May 2023 - Mar 2024
SystemVerilog Linter based on pyslang
Contributions:7 reviews, 81 PRs, 61 pushes in 10 months
svenka3/vunit
Jul 2017 - Aug 2023
Contributions:5 pushes in 6 years 2 months
testing-frameworkvhdltestingsystemverilogunit-testing-framework
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