Eduardo Castaño
Software Data Engineer
Cieza, Spain
Summary
👤
Senior🎓
Top SchoolEduardo Castaño is a software data engineer and researcher bridging data science with low-level systems engineering. He currently works at Revvity Signals, building data-driven software, with prior data science roles at Nunegal Consulting and TICARUM in Spain. He pursues PhD-level research in computer architecture across the Universidad de Murcia and the University of Uppsala, supported by his strong AI and big data foundations from Murcia. An active open-source contributor, he has implemented targeted fixes in the gem5 x86 simulator, improving instruction decoding, memory operation ordering, and ISA/microcode robustness. Fluent in English and proficient in Java and Python, he combines rigorous research with hands-on software development and agile practices.
11 years of coding experience
4 years of employment as a software developer
Spanish Bachelor of Science, Technology Science, Spanish Bachelor of Science, Technology Science at IES Diego TortosaMaster in Mass Data Analysis Technologies: Big Data, Big Data, 9.07, Master in Mass Data Analysis Technologies: Big Data, Big Data, 9.07 at Universidad de Murcia
English
Github Skills (14)
simulations10
simulation10
assembly10
architectures10
x86-6410
assemble10
assembler10
architecture10
x8610
c-programming-language9
debug9
c-language9
debugging9
risc-v4
Programming languages (8)
Github contributions (5)
gem5/gem5
Apr 2021 - Nov 2021
The official repository for the gem5 computer-system architecture simulator.
Role in this project:
Backend Developer
Backend DeveloperContributions:3 commits, 2 PRs, 4 comments in 7 months
Contributions summary:Eduardo primarily contributed to the x86 architecture simulation within the gem5 repository, focusing on fixing bugs related to instruction decoding and implementation. They addressed issues such as incorrect handling of segment registers and ensuring proper ordering of memory operations in the cmpxchg8b instruction. Additionally, the user fixed issues that were triggering asserts, improving the robustness of the x86 architecture simulation. The contributions involved modifying ISA files and microcode.
storedsimulationupstreamsimulatorgem5-simulator
OdnetninI/Splash-4
Mar 2021 - Mar 2023
The Splash-4 benchmark suite
Contributions:4 releases, 47 commits, 1 PR in 2 years
benchmarkbenchmarkssplash-3splash-4
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