Bipul Talukdar
Senior Director Of Engineering at Axiomise
San Jose, California, United States
Summary
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Rockstar🎓
Top SchoolBipul Talukdar is a San Jose–based Senior Director of Engineering who specializes in hardware functional verification, RISC-V, Verification IP architecture, formal property verification, emulation and clock-domain crossing. He has led VIP development and deployment across protocols such as PCIe, TileLink, AMBA and DDR while driving verification strategy at companies including Axiomise, Bluespec, SmartDV, SiFive, Cadence and Mentor. At SiFive he developed Chisel-based formal verification flows and notably worked to merge formal proof coverage into simulation coverage, presenting his work on parameterizable block-level FPV at the Chisel Community Conference. Bipul combines hands-on Chisel/Verilog/SystemVerilog and SVA coding with UVM and Python automation to deliver coverage-closure and emulation-ready solutions for complex SoCs. He is known for turning advanced formal and emulation techniques into customer-facing VIPs, training programs and business-driving applications.
8 years of coding experience
24 years of employment as a software developer
Cotton College, GuwahatiBachelor's degree, Electrical, Electronics and Communications Engineering, Bachelor's degree, Electrical, Electronics and Communications Engineering at National Institute of Technology SilcharBachelor of Engineering, Electronics and Telecommunications, Bachelor of Engineering, Electronics and Telecommunications at National Institute of Technology, Silchar
English, Hindi, Assamese, Sanskrit, Bengali
Github Skills (6)
chisel9
rocket-chip8
riscv8
scala8
rocket7
mcu1
Programming languages (2)
Github contributions (4)
bluespec/Tiny_TCM
Oct 2023 - Feb 2024
Contributions:2 pushes in 4 months
bluespec/mcu-release
Oct 2023 - Feb 2024
A release repository for the mcu class of CPUs
Contributions:3 pushes in 4 months
cpusmcu
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