Siddarth Goyal
ASIC Design Engineer at NVIDIA
Delhi, India
Summary
👤
Senior🎓
Top SchoolSiddarth Goyal is an ASIC Design Engineer at NVIDIA with a decade of experience in design verification and a specialization in formal verification methodologies. He leverages property checking and assertion-based verification using tools like JasperGold and VC Formal, collaborating closely with RTL and DV teams to ensure functional correctness at the IP and SoC level. He is passionate about integrating AI and large language models into EDA, researching Transformer-based models, retrieval augmented generation, and other techniques to accelerate hardware design and verification. Before NVIDIA, he contributed to data engineering and ML pipelines, including an 80% reduction in processing time for Apollo 24|7’s ETL pipeline, and built ML pipelines at Jocata using OpenCV, TensorFlow and Keras. Based in Delhi, India, he earned a BTech from IIT Delhi and has led international collaborations and events through the IIT Delhi alumni networks.
10 years of coding experience
1 year of employment as a software developer
Indian Institute of Technology Delhi (IIT Delhi)
Hindi
Github Skills (6)
vwo4
server-side2
testing2
python2
sdk1
a-b-testing1
Programming languages (2)
Github contributions (5)
sid3129/Coursera_Full_Stack_Web_Development
Dec 2015 - Jan 2016
Contributions:11 pushes, 1 branch in 22 days
sid3129/sample_website
Nov 2020 - Dec 2020
Contributions:10 pushes, 1 branch in 18 days
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