Summary
Aaditya Chaudhary is a Design Engineer specializing in ASIC/SoC/FPGA design and verification with a decade of hands-on experience spanning Verilog/SystemVerilog (UVM), C/C++, Python, and heterogeneous compute (CUDA/OpenCL). Currently at Ampere in Portland, he brings practical expertise in RTL development, verification, and CPU/GPU architecture informed by graduate research at NC State where he built a lightweight OpenCL runtime for FPGA/GPU scheduling. His background includes building and verifying bus-based cache coherence, MIPS-like pipelines, and ASIC implementations of neural primitives (LSTM/CNN), plus FPGA-based hardware-software coprocessors. Aaditya pairs toolchain fluency (Synopsys, Questasim, Xilinx Vivado) with embedded platform experience from Zynq and Virtex to Raspberry Pi, enabling cross-layer optimization from silicon to runtime. He also has entrepreneurial and research stints (IIM Bangalore incubatee, co-founder, and multiple academic internships), reflecting an ability to translate prototypical research into practical products.
10 years of coding experience
3 years of employment as a software developer
D.A.V Public School Bilaspur
Master of Science - MS, Computer Engineering, Master of Science - MS, Computer Engineering at North Carolina State University
Bachelor of Technology (B.Tech.), Electronics and Telecommunication Engineering, Bachelor of Technology (B.Tech.), Electronics and Telecommunication Engineering at National Institute of Technology Raipur
English, Hindi, Marathi