Aarush A is a Georgia Tech Computer Engineering junior (3.91 GPA) who builds across the full hardware–software stack, from SystemVerilog RTL and formal verification on FPGAs to embedded C++ firmware and high-level web services. He’s shipped RTL-to-GDSII flows and coherence logic for a tapeout at SiliconJackets, implemented a 2.33 Gbps XChaCha20 accelerator on Zynq UltraScale+, and architected a sub-12ms haptic insole as co-founder of TerraSense. His work blends practical product focus—prototype BOM and user testing—with rigorous verification (50+ assertions, constrained-random testbenches), and he’s also applied LLMs to automate student government finance workflows. Seeking internships in hardware design, embedded systems, or systems software, he brings rare end-to-end experience that accelerates projects from algorithm to silicon and back.
8 years of coding experience
2 years of employment as a software developer
Bachelor's degree, Computer Engineering, Bachelor's degree, Computer Engineering at Georgia Institute of Technology
Contributions:13 PRs, 27 pushes, 9 branches in 3 years 11 months
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Aarush A - Digital Design Engineer at SiliconJackets