Abarajithan G

Research Intern at AMD

San Diego, California, United States
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Summary

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Senior
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Top School
Abarajithan G is a PhD researcher in computer engineering at UCSD with nine years of hands-on experience in hardware security, SoC integration, and RTL design. Currently a research intern at AMD, he blends academic rigor from Kastner Research Lab with practical industry work at Qualcomm and Lemurian Labs, where he built compute cores, designed novel arithmetic for Multidimensional Logarithmic Number Systems, and automated CI/CD for RTL verification. He has led architectural evaluations of serialized bus architectures and created parameterized NOC bridge IPs, demonstrating a knack for marrying system-level trade-offs with implementation details. An experienced educator and organizer, he has taught digital design courses, mentored students, and co-founded a transparent, project-oriented foundation in Sri Lanka. Colleagues describe him as curious and quietly witty (his GitHub bio: "Mostly Harmless"), reflecting a pragmatic researcher who enjoys solving hard hardware-software problems.
code9 years of coding experience
job3 years of employment as a software developer
bookB.Sc (Hons), Electronics and Telecommunications Engineering, GPA: 3.92/4.2 = 3.86/4.0, First Class Honors, Deans List for 6/8 semesters, B.Sc (Hons), Electronics and Telecommunications Engineering, GPA: 3.92/4.2 = 3.86/4.0, First Class Honors, Deans List for 6/8 semesters at University of Moratuwa
bookUniversity of California, San Diego
bookHigh School, Physical Sciences, High School, Physical Sciences at St. Sylvester's College, Kandy
languagesEnglish, Tamil, Sinhala
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Stackoverflow

Stats
411reputation
17kreached
3answers
13questions
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Github Skills (90)

verilog10
asic10
axi-stream10
ai10
fpga10
systemverilog10
neural-network9
heatmap9
lattice9
cpp9
verilator9
polygon8
vivado8
contrast8
simulation8

Programming languages (10)

TypeScriptSystemVerilogC++CSCSSMakefileVerilogTcl

Github contributions (5)

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SkillSurf/systemverilog

Nov 2020 - Aug 2022

SystemVerilog for ASIC/FPGA Design & Simulation, with Synopsys Tool Flow
Contributions:20 commits, 56 pushes, 1 branch in 1 year 10 months
asicfpgasimulationsystemverilog
abarajithan11/cocotb-example

Mar 2022 - Jun 2022

Contributions:28 commits, 4 pushes, 1 branch in 2 months
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