Abhishek Vashist
Pixel IP Design Engineer (RTL) at Apple
City of Rochester, New York, United States
Summary
👤
Senior🎓
Top SchoolAbhishek Vashist is a Pixel IP Design Engineer at Apple with 10 years of experience bridging academic research and commercial silicon design, currently completing a PhD at Rochester Institute of Technology. His work spans RTL design for SoCs, mmWave radar and wireless systems, CPU microarchitecture and interconnects, and autonomous vehicle perception—research that earned an IEEE Best Paper Award at ICCE 2020. He has hands-on experience in custom ASIC/SoC design, C++/Python development, ROS-based edge ML, and platform ASIC work from internships at Google and Toyota Research. Based in Rochester, NY, Abhishek combines rigorous research publication credentials with practical system buildouts (including robotics and drone sensor integration) and a portfolio focused on autonomous vision systems. Notably, he teaches hardware design fundamentals and has a track record of turning complex signal-processing and V2V research into prototype hardware and software.
10 years of coding experience
5 years of employment as a software developer
Master’s Degree, Electrical Engineering & Computer Engineering - VLSI/Digital System Design, 3.68/4, Master’s Degree, Electrical Engineering & Computer Engineering - VLSI/Digital System Design, 3.68/4 at Rochester Institute of TechnologyBachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering, Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering at Dr. A.P.J. Abdul Kalam Technical University
English, Hindi
Github Skills (17)
systemverilog9
lidar8
rtl-design8
assertion8
uvm7
robotics7
camera7
dji-sdk7
trajectory-optimization7
testbench7
rover4
darknet4
sdk4
yolov43
tensorrt3
Programming languages (4)
Github contributions (5)
avashist003/UVM_Verification
May 2019 - Jun 2020
Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence
Contributions:12 commits, 11 pushes, 1 branch in 1 year 1 month
assertiontestbenchuvm
avashist003/SystemVerilog_Design_Verification
Jul 2022 - Aug 2022
Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog
Contributions:58 commits, 2 PRs, 53 pushes in 1 month
rtl-designsystemverilogrtldesign
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