AdamĀ Izraelevitz
Staff Engineer at SiFive
Berkeley, California, United States
Summary
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Top SchoolAdam Izraelevitz is a Staff Engineer based in Berkeley with 12 years of experience building and shipping hardware-focused compiler and RTL tooling. He holds a PhD-level background in EECS from UC Berkeley and a BS in Electrical and Computer Engineering from Cornell, combining deep research training with hands-on engineering. At SiFive he drives system-level design and compiler work, and his open-source contributions to the widely used FIRRTL compiler show expertise in type/width inference, circuit analysis, and Verilog generation. He also improves developer education, having restructured and authored Chisel bootcamp materials and Jupyter notebooks to make advanced hardware generators more approachable. Known for refactoring and optimizing complex codepaths, he blends rigorous correctness with practical code generation performance. Based in the Bay Area, he brings rare cross-disciplinary fluency between hardware design, compiler internals, and technical writing.
12 years of coding experience
Doctor of Philosophy (PhD), Electrical Engineering and Computer Science, Doctor of Philosophy (PhD), Electrical Engineering and Computer Science at University of California, BerkeleyBachelor of Science (B.S.), Electrical and Computer Engineering, Bachelor of Science (B.S.), Electrical and Computer Engineering at Cornell University
Github Skills (13)
verilog10
jupyter-notebook10
compiler-design10
firrtl10
documentation10
scala10
chisel9
type-inference9
test-driven-design8
code-generation8
bundle7
functional-programming7
object-oriented-programming6
Programming languages (8)
Github contributions (5)
chipsalliance/firrtl
Feb 2015 - Apr 2021
Flexible Intermediate Representation for RTL
Role in this project:
Back-end Developer
Back-end DeveloperContributions:35 reviews, 973 commits, 292 PRs in 6 years 3 months
Contributions summary:Adam contributed to the development of the Flexible Intermediate Representation for RTL (FIRRTL) compiler, specifically working on modules related to type and width inference, circuit analysis, and Verilog code generation. Their commits demonstrate the implementation of features, tests, and bug fixes related to handling SInts and Bundles within the FIRRTL compiler, ensuring correct behavior of the language. The commits also included refactoring and optimization efforts on the code base.
representationtransformationintermediate-representationrtlcompiler
freechipsproject/chisel-bootcamp
Jul 2017 - Oct 2020
Generator Bootcamp Material: Learn Chisel the Right Way
Role in this project:Technical Writer
Technical WriterContributions:1 review, 44 commits, 12 PRs in 3 years 2 months
Contributions summary:Adam's commits primarily focused on updating and adding content to the project's documentation, specifically in the form of Jupyter notebooks. The changes included adding a table of contents, clearing outputs, reorganizing the content, and integrating new sections on advanced Scala concepts. The user reorganized content from a separate file and incorporated a Chisel demo notebook, improving the tutorial's structure and usability for learners.
chiselhardwarevhdl
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