Adam Olech

Engineering Manager at Antmicro

Greater Poland Voivodeship
email-iconphone-icongithub-logolinkedin-logotwitter-logostackoverflow-logofacebook-logo
Join Prog.AI to see contacts
email-iconphone-icongithub-logolinkedin-logotwitter-logostackoverflow-logofacebook-logo
Join Prog.AI to see contacts

Summary

🤩
Rockstar
🎓
Top School
Adam Olech is an Engineering Manager with six years of hands-on experience in virtualization, distributed computing, embedded systems and web development, who has progressed through technical roles to lead teams at Antmicro. A full-time Linux user since 2014 and a linguistics enthusiast with an MA in English, he uniquely blends systems-level engineering with clear communication and documentation skills. He has strengthened CI/CD and automation for notable open-source tooling such as chipsalliance/verible, improving Bazel builds and automated docs generation. Based in Greater Poland, he pairs academic grounding in computer science with practical DevOps and cloud experience gained since internships in 2019. Colleagues rely on him for pragmatic automation improvements that make complex build and release processes more maintainable.
code6 years of coding experience
job4 years of employment as a software developer
bookBachelor of Engineering - B.Eng, Computer Science, 4.5, Bachelor of Engineering - B.Eng, Computer Science, 4.5 at Politechnika Poznańska
bookMaster of Arts - MA, English Language and Literature, General, Master of Arts - MA, English Language and Literature, General at Uniwersytet im. Adama Mickiewicza w Poznaniu
languagesEnglish, Polish, German, Norwegian
github-logo-circle

Github Skills (15)

automation10
github-ci10
bash10
automations10
githubaction-workflow10
bazel10
cicd10
makefile9
formatters7
systemverilog7
language-server-protocol7
parserator7
parser7
formatter7
linter7

Programming languages (10)

C#SystemVerilogCSSShellC++VerilogRobotFrameworkGo

Github contributions (5)

github-logo-circle
chipsalliance/verible

Nov 2022 - Jan 2023

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
Role in this project:
userDevOps Engineer / Automation Engineer
Contributions:15 reviews, 18 commits, 6 PRs in 1 month
Contributions summary:Adam focused on improving the continuous integration and continuous delivery (CI/CD) pipeline for the project. Their contributions included modifying build scripts, updating Bazel configurations, and automating the generation of documentation for the GitHub pages. The changes involved adjusting build processes, installing necessary dependencies, and setting up automated documentation generation using various tools. These modifications enhanced the automation and documentation aspects of the project.
lintersystemverilogdeveloper-toolsparserformatter
antmicro/dockersave

Mar 2020 - Feb 2023

Contributions:1 release, 10 commits, 24 pushes in 2 years 10 months
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.
Request Free Trial
Adam Olech - Engineering Manager at Antmicro