Adel Ejjeh is a Senior Member of Technical Staff and compiler architect with eight years of experience building LLVM/MLIR-based toolchains and high-level synthesis (HLS) flows for FPGA and spatial architectures. He has driven product- and architecture-level decisions—most recently leading the separation and redesign of Altera’s standalone HLS compiler—and focuses on tangible QoR wins (fmax, area, latency) alongside usability improvements like interpretable RTL and user reports. His background spans deep compiler transformations, SYCL/OpenCL accelerator programming, and end-to-end FPGA compilation from his PhD work at UIUC. Known for blending research-grade compiler design with product delivery, he mentors engineers and has published work that bridges academia and industry. Now at AMD, he continues to shape compiler infrastructure for unconventional compute targets out of Chicago.
9 years of coding experience
12 years of employment as a software developer
Lebanese baccalaureate General Sciences, Lebanese baccalaureate General Sciences at International College
Doctor of Philosophy (Ph.D.) Computer Science, Doctor of Philosophy (Ph.D.) Computer Science at University of Illinois Urbana-Champaign
Master of Engineering (MEng) Computer Engineering, Master of Engineering (MEng) Computer Engineering at American University of Beirut
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