Aditya Singh
Senior Design Verification Engineer
Bengaluru, Karnataka, India
Summary
👤
Senior🎓
Top SchoolAditya Singh is a Senior Design Verification Engineer with a decade of technical experience and over 3 years focused on PCIe IP verification using SystemVerilog and UVM. He has led test-plan definition, cross-team reviews, and implementation of testbenches and assertions to validate complex pre-silicon designs at Intel and now Synopsys. His background includes teaching and research at IIT Roorkee (MTech, 9.06 GPA), which informs a methodical approach to verification and mentorship. Aditya is interested in advancing verification for PCIe and emerging CXL standards and brings practical exposure to both industry and academic workflows. Although his GitHub presence centers on blockchain leadership, his day-to-day expertise remains firmly in hardware verification, bridging protocol-level rigor with system-level engineering.
10 years of coding experience
1 year of employment as a software developer
Indian Institute of Technology Roorkee
Hindi, Malayalam, English
Stackoverflow
944reputation
155kreached
20answers
38questions
Github Skills (26)
registers8
hyperledger8
ledger8
google-geocoding-api6
hash6
google-maps-api6
distributed-ledger6
geocoding6
ethereum6
google-maps6
blockchain6
scada6
python6
git6
dlt5
Programming languages (3)
Github contributions (5)
adityasingh177/sawtooth-core
Mar 2018 - Jan 2019
Core repository for Sawtooth Distributed Ledger
Contributions:6 PRs, 159 pushes, 28 branches in 10 months
distributed-ledgersawtoothledgerdistributed
block-exchange/web
Sep 2020 - Mar 2021
Web Front for Exchange
Contributions:54 PRs, 129 pushes, 4 branches in 6 months
ethereumreactblockchainexchange
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.