Summary
Aditya Singhal is a GPU architecture engineer with about a decade of hands-on experience in low-level firmware, device drivers, and hardware modeling, currently contributing to the Load-Store Cache subsystem of Intel’s XE4 graphics IP. He has a strong background in SystemC/TLM modelling and Simics-based hardware simulation from roles at Intel, Altera/PSG, and Vayavya Labs, and has driven FPGA IP and NoC/memory-controller co-design for early software bring-up. Early career work in embedded systems and robotics gave him practical expertise in ARM microcontrollers, sensor integration, and real-time firmware for defense and robotics applications. He holds an MTech in Microelectronics from BITS Pilani and a C-DAC diploma in embedded systems, blending formal training with applied engineering. Colleagues value his ability to move between assembly-level optimization and high-level architectural modeling, and he brings a curious, outdoors-ready mindset—he’s an avid trekker and table-tennis player who enjoys learning new technologies.
9 years of coding experience
9 years of employment as a software developer
BITS Pilani, Birla Institute of Technology and Science
PG Diploma Embedded Systems and Design, PG Diploma Embedded Systems and Design at Centre for Development of Advanced Computing (C-DAC)
Bachelor of Technology (B.Tech.) Electronics and Communications Engineering, Bachelor of Technology (B.Tech.) Electronics and Communications Engineering at Jaypee University of Engineering and Technology
XII, XII at Ch. Chabbil Dass public School
English, Hindi