Adrian Costina
Senior Manager, FPGA Development at Analog Devices
Cluj-Napoca, Romania
Summary
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Rockstar🎓
Top School
Top expert inDigital Hardware Design and Verification
Adrian Costina is a Senior Manager in FPGA Development based in Cluj-Napoca with 12 years of experience designing and leading FPGA and embedded systems across Xilinx, Intel/Altera, and Versal platforms. At Analog Devices he has grown and managed multi-disciplinary FPGA teams while contributing hands-on to open-source no-OS projects, implementing drivers and JESD204B-capable ADC integrations for high-speed data acquisition. His background spans RTL design, system-level synchronization of ADCs, SPI/JESD interfaces, and embedded C for bare-metal systems—skills honed through earlier roles building HDL reference designs and automated test tooling. Known for blending technical depth with people leadership, he pairs a strong academic record in electronics engineering with practical experience shipping evaluation platforms and production-ready FPGA designs.
12 years of coding experience
13 years of employment as a software developer
Master' degree, Electronics enginnering, 9.41/10, Master' degree, Electronics enginnering, 9.41/10 at Universitatea Tehnică din Cluj-Napoca
English, German
Github Skills (12)
c1710
embedded10
serial-communication10
device-driver10
abstraction-layer10
c1110
spi10
sys10
hal10
jes10
zynq7
microblaze7
Programming languages (4)
Github contributions (5)
analogdevicesinc/no-OS
Feb 2017 - Sep 2017
Software drivers in C for systems without an operating system
Role in this project:
Embedded Systems Engineer / IoT Developer
Embedded Systems Engineer / IoT DeveloperContributions:1 review, 9 commits, 5 pushes in 7 months
Contributions summary:Adrian's contributions primarily involve implementing and updating software drivers for Analog Devices' no-OS systems. They focused on initializing and configuring various hardware components, including AD9625 and AD9250 analog-to-digital converters (ADCs). The user demonstrated expertise in setting up SPI communication, configuring JESD204B interfaces, and integrating with hardware platforms. They also added functionality for synchronizing multiple AD9625 ADCs, which highlights their understanding of system-level design and real-time constraints.
driveroperating-systemdevice-driveranalog-devicesno-os
acostina/hdl
Jan 2021 - Jun 2023
HDL libraries and projects
Contributions:24 pushes, 18 branches in 2 years 5 months
hdl
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