Adrian Fiergolski
Senior ASIC Design Engineer at CERN
Lausanne, Vaud, Switzerland
Summary
👤
Senior🎓
Top SchoolAdrian Fiergolski is a Senior ASIC Design Engineer with 13 years of experience building and verifying complex digital systems for high-energy physics and commercial LiDAR applications. He has led SoC and MPSoC projects from architecture through silicon-focused verification, leveraging SystemVerilog, UVM/UVMF, emulation, and HLS alongside FPGA and embedded Linux development. At CERN he drove UVM-based verification for pixel-detector ASICs and built versatile DAQ frameworks and firmware, while at Fastree3D he combined ASIC/FPGA design with CI/CD, AWS-based IT management, and delivery of flash LiDAR demonstrators. Now working on RISC-V SoC implementations for HEP at CERN in Lausanne, he blends deep hardware verification expertise with low-level software and system integration skills. Known for shipping pragmatic, emulation-friendly verification environments and creating tooling such as HDLMake, he brings a research-grade PhD background to fast-moving product and R&D teams.
13 years of coding experience
7 years of employment as a software developer
Doctor of Philosophy - PhD Electronics and Computer Engineering, Doctor of Philosophy - PhD Electronics and Computer Engineering at Warsaw University of Technology
Polish, English
Stackoverflow
11reputation
62reached
0answers
1question
Github Skills (13)
fpga10
embedded10
server-configuration10
configurations10
u-boot10
system-configuration10
zynqmp10
sys10
hardware10
cprogramming-language9
i2c9
python6
twisted6
Programming languages (12)
Github contributions (5)
adrianf0/meta-xilinx
Nov 2019 - Jun 2024
Xilinx device and board support for Yocto/OE-core.
Contributions:23 pushes, 18 branches in 4 years 7 months
xilinxboardyocto
adrianf0/calibre
Dec 2015 - Aug 2018
The official source code repository for the calibre ebook manager
Contributions:9 pushes in 2 years 8 months
ebookrequirements-managementheadcode-repositoryebook-manager
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