Aidan Klein

Digital Engineer at Northrop Grumman

Hanover, Maryland, United States
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Summary

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Aidan Klein is a Digital Engineer with nine years of hands-on experience designing and implementing hardware-software systems, currently contributing at Northrop Grumman from Hanover, Maryland. He blends digital design expertise in Verilog, SystemVerilog and VHDL with software skills including Linux kernel module development and Python, having built drone firmware and custom board support at CraftDrones. Aidan is an active back-end contributor to the Scala-based SpinalHDL project, improving HDL emission, test suites, and reusable data structures—work that underscores his deep understanding of hardware description languages and build tooling. Comfortable moving between low-level hardware RTL and higher-level software infrastructure, he brings practical systems thinking and a track record of reducing duplication and hardening build processes.
code9 years of coding experience
job1 year of employment as a software developer
bookComputer Engineering Technology, Computer Engineering Technology/Technician, Computer Engineering Technology, Computer Engineering Technology/Technician at Rochester Institute of Technology
bookAssociate of Arts and Sciences (AAS), Electrical Engineering Technology, Associate of Arts and Sciences (AAS), Electrical Engineering Technology at Broome Community College
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Github Skills (5)

scala10
system-design8
version-control7
git7
test-framework6

Programming languages (5)

TypeScriptC++RustScalaPython

Github contributions (5)

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SpinalHDL/SpinalHDL

Feb 2021 - Jan 2023

Scala based HDL
Role in this project:
userBack-end Developer
Contributions:35 reviews, 244 commits, 75 PRs in 1 year 11 months
Contributions summary:Aidan primarily contributed to the development of the SpinalHDL library. Their commits focused on improving the codebase, including fixing build-related issues, making source code directory management more robust, and extending the data structures through the addition of a Suffixable trait to reduce code duplication and increase reusability. The user also focused on VHDL and Verilog emission and struct handling, demonstrating a strong understanding of hardware description languages. They were also focused on integrating a new test suite framework.
scalartlvhdlverilogfpga
kleinai/SpinalHDL

Feb 2021 - Aug 2023

Scala based HDL
Contributions:216 pushes, 64 branches in 2 years 6 months
scalahdl
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