Aishwarya Gandhi
Sr. ASIC Design Engineer at NVIDIA
Stony Brook, New York, India
Summary
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Senior🎓
Top SchoolAishwarya Gandhi is a Sr. ASIC Design Engineer with eight years of experience specializing in RTL/ASIC design and verification, computer architecture, and high-performance microarchitecture for processor cores. Currently at NVIDIA, she has led RTL implementation for deep-pipelined, multi-issue cores—owning execution units, fetch/decode, load/store, pipeline control and structural MAC design—while balancing performance, area and power trade-offs. She is proficient in SystemVerilog and Synopsys toolchains (VCS, DC, Verdi) and routinely bridges architecture and implementation through micro-architecture specs, synthesis, LEC and STA. Her background includes hands-on verification, creating assembly tests and local testbenches, and designing cache/local memory and branch prediction features. An M.S. electrical engineering candidate at Stony Brook with prior sensor and embedded-system internship experience, she brings both analog-sensor insight and digital-core rigor. Notably, she has a track record of improving scalar core efficiency by architecting structural MAC units and integrating new coprocessor functionality into production designs.
8 years of coding experience
5 years of employment as a software developer
Bachelor of Engineering - BE, Electronics and Telecommunication, Bachelor of Engineering - BE, Electronics and Telecommunication at Maharashtra Institute of TechnologyMasters, Electrical Engineering, Masters, Electrical Engineering at Stony Brook University
English, Hindi, MarathiGithub contributions (5)
AishwaryaGandhi/Advanced-VLSI-Systems-Design-Coursework-Project
Feb 2018 - Feb 2018
Contributions:13 commits, 12 pushes, 1 branch in 1 day
AishwaryaGandhi/Advanced-Digital-System-Design-Generation
Feb 2018 - Feb 2018
Contributions:17 pushes in 1 day
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