Ajaykumar Kannan
Software Development Manager at Amazon Web Services (AWS)
Old Toronto, Ontario, Canada
Summary
🤩
Rockstar🎓
Top SchoolAjaykumar Kannan is a software development manager with 13 years of experience leading compiler and accelerator-focused engineering teams, currently building machine learning compilers for AWS Inferentia and Trainium. Previously he led Intel’s oneAPI compiler efforts for FPGAs in Toronto, shaping LLVM-based HLS and OpenCL toolchains and driving SYCL 2020–aligned changes in public oneAPI samples. He blends hands-on compiler engineering with people leadership, shipping production-ready FPGA and AI-accelerator toolchains at scale. Comfortable in both research-adjacent roles and product delivery, he holds an MASc in Computer Engineering from the University of Toronto and began his career in VLSI and embedded systems. An active contributor to oneAPI sample code, he’s focused on practical portability and simulator support that smooth FPGA developer onboarding.
14 years of coding experience
9 years of employment as a software developer
CMR National Public SchoolBachelor of Technology, Electronics and Communications Engineering, Bachelor of Technology, Electronics and Communications Engineering at Indian Institute of Technology, GuwahatiMaster of Applied Science, Computer Engineering, Master of Applied Science, Computer Engineering at University of TorontoITI Central School
English, Tamil
Stackoverflow
313reputation
25kreached
3answers
3questions
Github Skills (14)
fpga10
sycl10
oneapi10
c-language10
cprogramming-language10
headers9
xcode6
cuda6
macports6
macos6
serial-port6
android6
arduino6
serialization6
Programming languages (6)
Github contributions (5)
oneapi-src/oneAPI-samples
Apr 2021 - Oct 2022
Samples for Intel® oneAPI Toolkits
Role in this project:
Back-end Developer
Back-end DeveloperContributions:14 reviews, 10 commits, 20 PRs in 1 year 6 months
Contributions summary:Ajaykumar primarily worked on the Intel oneAPI samples repository, making changes related to FPGA development and SYCL. Their contributions involved modifying code to incorporate SYCL 2020 standards, specifically changing header includes and namespaces from INTEL to ext::intel. They also addressed issues with attributes like `initiation_interval` and `noinit` and added simulator targets to tutorials. These changes indicate a focus on adapting and improving code for FPGA compilation and execution within the oneAPI framework.
oneapiaicpucudafortran
ajaykumarkannan/llvm
Jun 2020 - Oct 2022
Intel staging area for llvm.org contribution. Home for Intel LLVM-based projects.
Contributions:1 review, 1 PR, 64 pushes in 2 years 4 months
staginginteloneapillvm
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.