Akhil Baranwal
HLS Design Engineer at Qualcomm
Greater Vancouver Metropolitan Area Canada
Summary
👤
Senior🎓
Top SchoolAkhil Baranwal is an HLS design engineer with nine years of experience bridging software compilers and RTL hardware for accelerator systems, currently working at Qualcomm after research and prototyping roles at HiAccel Lab and Simon Fraser University. He has hands-on experience across ASIC and FPGA flows—spanning uncore CPU design, UFS storage controller verification, HAL development, and post-silicon validation—which gives him a rare full-stack perspective from compiler optimizations down to behavioral RTL. His academic work and guest research in scalable reinforcement-learning accelerators reflect a sustained interest in architecture for machine learning, while his teaching roles highlight an ability to translate complex heterogeneous-computing concepts to others. Based in Greater Vancouver, he blends a maker’s mentality with deep computer-architecture curiosity and an openness to neuro-inspired hardware ideas that inform unconventional accelerator designs.
9 years of coding experience
6 years of employment as a software developer
BITS Pilani, Birla Institute of Technology and ScienceAISSCE, Maths + Science, AISSCE, Maths + Science at Delhi Public School GhaziabadMaster of Applied Sciences - MASc, Computer Engineering, Master of Applied Sciences - MASc, Computer Engineering at Simon Fraser University
Github Skills (5)
xtensa10
esp82668
automation4
esp322
esp-idf1
Programming languages (5)
Github contributions (5)
SFU-HiAccel/pasta
Sep 2023 - Jun 2025
[FCCM 2023] PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs
Contributions:3 reviews, 8 PRs, 10 pushes in 1 year 9 months
automation
thecurryspice/vms
Jun 2018 - Jul 2020
Contributions:29 commits, 21 pushes, 2 branches in 2 years 1 month
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