Albert Chen
Software Engineer at SiFive
Berkeley, California, United States
Summary
🤩
Rockstar🎓
Top SchoolAlbert Chen is a software engineer and UC Berkeley computer science student with seven years of hands-on experience in low-level programming, compiler engineering, and hardware design. He contributes to high-profile open-source projects in the Chips Alliance ecosystem—notably Chisel, FIRRTL, and Rocket Chip—where he implemented and optimized constant propagation and improved Verilog emission for better performance and debuggability. At Berkeley Lab he helped port and extend system generators, integrate variable-precision DSP blocks into Rocket FPU flows, and built Verilator test harnesses, reflecting a strong bridge between research and production hardware tooling. Currently at SiFive, he applies that compiler-to-hardware expertise to commercial RISC-V core development, combining academic rigor with practical system engineering. Colleagues value his ability to translate formal compiler optimizations into tangible improvements in hardware generators and emitter performance.
7 years of coding experience
Bachelor’s Degree, Computer Science, 3.776, Bachelor’s Degree, Computer Science, 3.776 at University of California, Berkeley
English
Github Skills (20)
verilog10
generator10
firrtl10
scala10
compiler-design10
optmization10
performance-optimization10
optimisation10
chisel10
rt10
compiler-optimization10
chip810
optimization10
risc-v9
intermediate-code9
Programming languages (10)
Github contributions (5)
chipsalliance/firrtl
Jul 2018 - Jun 2021
Flexible Intermediate Representation for RTL
Role in this project:
Back-end Developer & Compiler Engineer
Back-end Developer & Compiler EngineerContributions:2 reviews, 52 commits, 45 PRs in 2 years 10 months
Contributions summary:Albert contributed significantly to the Firrtl compiler project by implementing and optimizing constant propagation, a crucial compiler optimization technique. Their work included adding constant propagation for specific operations (add, and, or, xor, and bit extraction), adding associated tests, and improving the performance of the Verilog emitter. They also refactored code to use a LinkedHashSet for annotation processing and added functionalities for emitting Verilog comments to describe nodes, which improves the code readability and debugging processes.
representationtransformationintermediate-representationrtlcompiler
chipsalliance/rocket-chip
Sep 2018 - Nov 2020
Rocket Chip Generator
Role in this project:Backend Developer
Backend DeveloperContributions:2 reviews, 152 commits, 36 PRs in 2 years 2 months
Contributions summary:Albert primarily contributed to the backend logic of the Rocket Chip Generator, as evidenced by code changes in FPU and RocketCore modules. These commits focused on making signals public, fixing whitespace, and refactoring code within the system generator. The user also updated build rules and added features related to the system generator.
rtlriscvchipchiselscala
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.