Aleš Svetek
Founder And CEO at AddigiSys
Slovenia
Summary
👤
Senior🎓
Top SchoolAleš Svetek is a founder and CEO with a decade of hands-on experience in high-speed FPGA design, hardware/software co-development, and embedded systems. He built AddigiSys after nearly a decade of R&D engineering at institutions including CERN and the Jozef Stefan Institute, bringing research-grade rigor to product development. His strengths include RTOS integration, device driver development, and applying test-driven development practices to low-level firmware and hardware projects. Trained as an electrical engineer (MSc) at the University of Ljubljana, he combines academic depth with entrepreneurial execution. Based in Slovenia, he quietly specializes in squeezing deterministic performance from constrained embedded platforms—often a differentiator in industrial and physics-driven applications.
10 years of coding experience
10 years of employment as a software developer
Masters, Electrical Engineering (Electronics), Masters, Electrical Engineering (Electronics) at University of Ljubljana
Github Skills (15)
dub10
vivado10
vhdl9
tcl9
makefile9
lattice9
asic9
fpga9
hdl9
build-system8
firmware8
python7
trigger6
cms4
typescript2
Programming languages (2)
Github contributions (5)
APxL1TAlgoDev/ctp7_hls_proj
Aug 2018 - Oct 2018
Contributions:10 commits, 7 pushes, 1 branch in 1 month
asvetek/ruckus
Aug 2018 - Dec 2019
Vivado build system
Contributions:8 pushes in 1 year 3 months
vivadobuild-systembuild-tool
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