Alex Forencich
Project Scientist at FPGA Ninja, LLC
San Diego, California, United States
Summary
🤩
Rockstar🎓
Top SchoolAlex Forencich is a project scientist and FPGA-focused hardware engineer with 16 years of experience designing embedded systems, firmware, PCB layouts, and high-performance datacenter networking. Based in San Diego, he holds a Ph.D. in electrical engineering from UC San Diego and has progressed from graduate researcher to postdoc and now project scientist while also founding FPGA Ninja, LLC. He is a prolific open-source contributor of Verilog modules and NIC platform work—maintaining well-regarded projects for AXI, AXI-Stream, I2C, Ethernet, and the Corundum FPGA NIC used for in-network compute. Alex blends low-level Verilog design and testbench-driven verification with system-level integration (Wishbone/AXI, XGMII) and practical hardware debugging, often adding protocol features and robustness fixes. Beyond code, his background includes hands-on hardware prototyping, GT refactors for high-speed interfaces, and leadership of student hardware teams, reflecting a rare combination of academic research depth and production-ready engineering.
16 years of coding experience
14 years of employment as a software developer
University of California, San DiegoElectrical Engineering, Electrical Engineering at Tohoku University
Stackoverflow
1,375reputation
379kreached
37answers
1question
Github Skills (23)
udp10
verilog10
python10
axi410
ethernet10
i2c10
digital-design10
ax10
sys10
fifo10
fpga10
hdl10
embedded10
testbench10
rg9
Programming languages (24)
Github contributions (5)
alexforencich/verilog-axi
Jul 2018 - Sep 2022
Verilog AXI components for FPGA implementation
Role in this project:
Backend Developer
Backend DeveloperContributions:176 commits, 124 pushes, 4 branches in 4 years 2 months
Contributions summary:Alex appears to be focused on implementing and fixing issues related to the Verilog AXI components for FPGA implementation. The commits show the user correcting issues related to address boundary assertions, implementing support for omitting ID signals, and updating aspects to support python 2 updates. They also improved the testbench and added parameter support for burst lengths and channel pausing.
fpgaverilog
alexforencich/verilog-i2c
Apr 2015 - Jun 2021
Verilog I2C interface for FPGA implementation
Role in this project:Embedded Systems Engineer
Embedded Systems EngineerContributions:38 commits, 19 pushes, 1 branch in 6 years 3 months
Contributions summary:Alex primarily contributed to the development of a Verilog I2C interface for FPGA implementation. Their work involved updating comments, modifying existing Verilog code, and adding new features such as an explicit I2C stop command. They also integrated Wishbone and AXI stream endpoints and created testbenches, and implemented various test cases within python.
fpgai2cverilog
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