Alex Levenzon
Senior Physical Design Engineer at Intel Corporation
Portland, Oregon, United States
Summary
👤
Senior🎓
Top SchoolAlex Levenzon is a Senior Physical Design Engineer with over 20 years in VLSI and nine years in senior roles, specializing in floorplanning, P&R, timing closure and low-power optimization for CPU and SoC designs. He has led high-complexity, timing-critical partitions and chip-level PnR efforts at Intel and Apple, driving methodology improvements that bridge FE RTL teams and backend physical design. Deep hands-on expertise with Synopsys Fusion/ICC/DC/Power Compiler and Cadence Genus/Innovus/Voltus underpins his ability to resolve severe routing congestion, IR drop and timing challenges across multi-power-domain blocks. Alex blends circuit-level insight—having designed custom memories, register files and critical IP—with data-driven power analysis tooling he helped develop for CPU cores. Based in Portland and educated at Technion, he pairs rigorous silicon-proven delivery with a knack for creating collaborative flows that accelerate cross-team fixes.
9 years of coding experience
21 years of employment as a software developer
Bachelor of Science (BSc), Electrical and Electronics Engineering, Bachelor of Science (BSc), Electrical and Electronics Engineering at Technion - Israel Institute of Technology
English, Hebrew, Russian
Github Skills (4)
eclipse-plugin10
refactoring10
java9
accessibility1
Programming languages (1)
Github contributions (5)
TechnionYP5777/Leonidas-FTW
May 2017 - Jul 2017
Leonidas FTW
Contributions:72 commits, 33 pushes, 17 comments in 1 month
SharonKL/Spartanizer
Oct 2016 - Oct 2016
Contributions:1 push in 1 day
mavenreadableeclipse-pluginjava-sourcerefactoring
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