Alexandr Lapin
FPGA Engineer at Deleted
Russia
Summary
👤
Senior🎓
Top SchoolAlexandr Lapin is an FPGA Engineer with a decade of hands-on experience designing and optimizing RTL in SystemVerilog, Verilog and VHDL for high-performance applications. He has proven expertise in testbench development (QuestaSim/ModelSim with UVM familiarity), high-speed transceivers (GTP/GTH) and working with ADC/DAC families such as AD9172, AD9691 and ADRV9002. Alexandr translates DSP algorithms from MATLAB/Simulink into HDL and C, leveraging automated code generation to accelerate development cycles and improve performance through pipelining and resource-aware placement. He maintains disciplined version control with Git/SVN and has applied his skills in both industry and applied research settings in Russia. Colleagues rely on him to squeeze extra performance and efficiency from complex FPGA designs while preserving verifiable test coverage.
10 years of coding experience
2 years of employment as a software developer
Магистр, Радиотехника, 4,2, Магистр, Радиотехника, 4,2 at ВГТУ
Github Skills (20)
server-side-rendering9
python8
component-library8
elasticsearch-client8
ui-components7
omniauth7
ruby7
ruby-client7
api7
oauth6
devise6
rails6
authentication6
token-based-authentication6
json4
Programming languages (1)
Github contributions (5)
Xanderwot/phlex
Aug 2024 - Sep 2024
A framework for building object-oriented views in Ruby.
Contributions:7 pushes, 1 branch in 2 days
Xanderwot/depot-angular
Jul 2016 - Jul 2016
Contributions:4 pushes, 1 branch in 3 days
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