Alexandrea Demmings
Software Developer at Gastops
Ottawa, Ontario, Canada
Summary
🤩
Rockstar🎓
Top SchoolAlexandrea Demmings is a software developer with eight years of experience, currently applying her engineering skills at Gastops in Ottawa after graduating in Computer Software Engineering from UNB. She has a strong systems and back-end focus evidenced by her work on the open-source Verilog-to-Routing project, where she tracked down memory leaks, double frees, and uninitialized values to improve stability of an FPGA CAD flow. Her background spans academic research and teaching—supporting HCI input-method studies and instructing first-year programming—as well as community-facing roles teaching coding to youth, showing she communicates technical ideas clearly to diverse audiences. Comfortable debugging low-level issues and shipping reliable code, she blends practical engineering with a knack for making complex systems more robust.
8 years of coding experience
1 year of employment as a software developer
Bachelor's degree, Computer Software Engineering, Bachelor's degree, Computer Software Engineering at University of New Brunswick
French, English
Github Skills (8)
memory-management10
debug10
verilog10
c-language10
cprogramming-language10
eda9
cad9
fpga9
Programming languages (3)
Github contributions (5)
verilog-to-routing/vtr-verilog-to-routing
Jan 2019 - Aug 2019
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Role in this project:
Back-end Developer
Back-end DeveloperContributions:230 commits, 142 PRs, 40 pushes in 7 months
Contributions summary:Alexandrea primarily focused on fixing memory leaks and other bugs within the Verilog-to-Routing (VTR) project. Their contributions involved code modifications in several source files related to pre-processing Verilog code, creating and manipulating netlists from the AST, and managing implicit memory. They addressed issues such as double frees, uninitialized values, and string-related memory leaks, improving the overall stability and correctness of the codebase.
vtrcadedaplacementsynthesis
ademmings/vtr-verilog-to-routing
Jan 2019 - Jul 2019
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Contributions:124 pushes, 119 branches in 5 months
cadedasynthesisplacementrouting
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