Alick Wang
Pixel IP Design Engineer at Apple
Cupertino, California, United States
Summary
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Senior🎓
Top SchoolAlick Wang is a Pixel IP Design Engineer at Apple with nine years of SoC and ASIC design experience spanning DMA, memory subsystems, cache-coherent fabrics, and display pixel processing. He brings deep hands-on expertise across micro-architecture, RTL (Verilog/SystemVerilog/UVM), formal verification, synthesis and timing closure, and has driven flow automation and design-data analysis with Python and Tcl. Prior roles at Intel and Marvell include designing UPI snoop filters, link-layer datapaths, and high-performance DDR controllers, demonstrating a track record of reducing latency and meeting GHz-class timing targets. Comfortable across EDA toolchains (Synopsys, Cadence, Dorado) and industry specs (PCIe, AXI, UPI, LPDDR/DDR), he blends low-level digital design with system-level integration. Based in Cupertino with an MS from UCLA and a BS from Fudan, he pairs rigorous academic training with pragmatic engineering impact. Beyond pixel IP, he’s intrigued by big-data technologies, signaling a broader interest in scalable data-driven design and analysis.
9 years of coding experience
4 years of employment as a software developer
Bachelor of Science (B.S.) in Microelectronics, Integrated Circuits and Electronics Engineering, 3.46/4.00, Bachelor of Science (B.S.) in Microelectronics, Integrated Circuits and Electronics Engineering, 3.46/4.00 at Fudan UniversityMaster of Science (M.S.) in Electrical Engineering, Integrated Circuits and Embedded System, 3.88/4.00, Master of Science (M.S.) in Electrical Engineering, Integrated Circuits and Embedded System, 3.88/4.00 at University of California, Los Angeles
Chinese, EnglishGithub contributions (5)
comestime/Cousera-Algorithm-Programming-Assignment
May 2017 - Sep 2017
Contributions:71 commits, 65 pushes, 1 branch in 4 months
comestime/MacOS_Settings
May 2017 - Feb 2025
Contributions:21 pushes, 1 branch in 7 years 11 months
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