Alin-tudor Sferle
System Design Engineer at Analog Devices
Romania
Summary
🤩
Rockstar🎓
Top SchoolAlin-tudor Sferle is a System Design Engineer with six years of hands-on experience designing and verifying FPGA-based solutions at Analog Devices, specializing in SoC integrations for ADCs, RF transceivers and Ethernet PHYs. He combines firmware, HDL (SystemVerilog) and Linux bringup skills with scripting in Python, TCL, Perl and Bash to deliver reference designs and verification infrastructure. His open-source contributions to Analog Devices' HDL repositories show a practical focus on debugging register mismatches, restoring regmap behavior and adding Xilinx symbol operation support—evidence of both low-level hardware fluency and careful testbench work. Currently pursuing a PhD in Computer Networks while holding a master's in Telecommunications Engineering, he brings research rigor to applied system design. Colleagues know him for bridging prototype bring-up to production-grade verification and for mentoring students in technical skills beyond classroom theory.
6 years of coding experience
Master's degree, Telecommunications Engineering, Master's degree, Telecommunications Engineering at Technical University of Cluj-NapocaNational College "Onisifor Ghibu"Doctor of Philosophy - PhD, Computer Networks, Doctor of Philosophy - PhD, Computer Networks at Technical University of Cluj Napoca
Stackoverflow
29reputation
4kreached
0answers
5questions
Github Skills (14)
hdl10
fpga10
testbed10
embedded10
testbench10
sys10
xilinx9
verilog9
git6
bash6
dictionary6
github6
numpy6
bitbucket6
Programming languages (9)
Github contributions (5)
analogdevicesinc/hdl
May 2021 - Jan 2023
HDL libraries and projects
Role in this project:
Embedded Systems Engineer
Embedded Systems EngineerContributions:77 reviews, 23 commits, 65 PRs in 1 year 7 months
Contributions summary:Alin-tudor primarily addressed register mismatches and configuration issues within testbenches, focusing on the `axi_dmac`, and `jesd204` components. They corrected register settings in the `regmap_tb` testbench for the `dmac_tb` and `jesd204` designs, and also restored the `axi_dmac_regmap_request` to a previous version, indicating a focus on debugging and ensuring the correct functionality of the hardware components. Additionally, the user added support for symbol operation mode on Xilinx devices by modifying the core and related interfaces, which suggest they work with system-on-chip (SoC) design.
fpgaasicjesd204bhdlvhdl
alin724/testbenches
Apr 2021 - Sep 2021
Testbenches for HDL projects
Contributions:120 pushes, 20 branches in 5 months
testinghdl
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