Aman Arora
Assistant Professor at Arizona State University
Tempe, Arizona, United States
Summary
🤩
Rockstar🎓
Top SchoolAman Arora is an Assistant Professor and FPGA/ML systems researcher with six years of industry and academic experience spanning NVIDIA, UT Austin, and Arizona State University. He blends deep hardware design and verification expertise from GPU and SoC projects with recent research on FPGA architectures optimized for deep learning, including contributions that model TPU-like accelerators. His open-source work on the prominent VTR Verilog-to-Routing CAD flow includes developing ML benchmarking designs and Verilog integrations to evaluate accelerator architectures. Based in Tempe, he brings a rare mix of production-grade engineering and academic rigor, mentoring students while driving practical hardware/software co-design for AI.
6 years of coding experience
13 years of employment as a software developer
Doctor of Philosophy - PhD, Computer Engineering, FPGA, Reconfigurable Computing, Machine Learning, Deep Learning, MS, Electrical and Computer Engineering, B.Tech., Electronics & Communication Engineering, Doctor of Philosophy - PhD, Computer Engineering, FPGA, Reconfigurable Computing, Machine Learning, Deep Learning, MS, Electrical and Computer Engineering, B.Tech., Electronics & Communication Engineering at The University of Texas at Austin
The University of Texas at Austin
Hindu Vidyapeeth, Sonepat
English
Github Skills (6)
fpga10
verilog10
machine-learning10
eda9
cad9
deep-learning9
Programming languages (3)
Github contributions (5)
verilog-to-routing/vtr-verilog-to-routing
Oct 2020 - Nov 2022
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Role in this project:
ML Engineer
ML EngineerContributions:22 reviews, 80 commits, 15 PRs in 2 years 1 month
Contributions summary:Aman primarily contributed to the development of benchmarks for machine learning, specifically targeting Google's TPU-like architectures. Their work included adding new benchmarks, like the TPU (Tensor Processing Unit), and creating new designs that mimicked TPU functionalities for ML benchmarking. The user's contributions involved writing and modifying Verilog code and documentation to support the integration of these new designs within the VTR (Verilog-to-Routing) framework.
vtrcadedaplacementsynthesis
UT-LCA/tpu_v2
Jan 2021 - Apr 2022
Contributions:54 commits, 2 PRs, 45 pushes in 1 year 3 months
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