Amarnath Mahadevuni
Senior Design Verification Engineer
Durham, North Carolina, United States
Summary
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Senior🎓
Top SchoolAmarnath Mahadevuni is a Senior Design Verification Engineer with 10 years of experience specializing in translating complex hardware specifications into robust verification plans and implementing constrained-random stimulus and checkers using C++ and SystemVerilog/UVM. At NVIDIA he has owned verification features for GPU memory subsystems, extended testbench interfaces in Verilog, and maintained an internal C++ library for process address space mapping, routinely triaging nightly regressions to pinpoint test, checker, or DUT faults. His background at Cadence and graduate work at Texas A&M sharpened his expertise in storage protocols and verification IP, blending protocol-level rigor with practical test infrastructure development. Known for clear cross-team communication, he keeps verification plans aligned with evolving specs while pushing automation and reusable infrastructure. Colleagues rely on him to turn ambiguous hardware requirements into targeted, debuggable verification coverage that reduces time-to-root-cause in large regression suites.
10 years of coding experience
2 years of employment as a software developer
Indian Institute of Technology RoorkeeHigh School, Mathematics, Physics, and Chemistry, 95.7%, High School, Mathematics, Physics, and Chemistry, 95.7% at Sri Chaitanya Juinior KalasalaTexas A&M University
EnglishGithub contributions (5)
amarnathmhn/4-core-MESI-Cache-Verification
Dec 2015 - Jan 2017
Contributions:25 commits, 19 pushes, 1 branch in 1 year 1 month
amarnathmhn/project-wishlist
Apr 2017 - Oct 2020
Contributions:4 pushes, 1 branch in 3 years 6 months
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