Anandh Venkateswaran
Machine Learning Compiler Engineer at Amazon Web Services (AWS)
Old Toronto, Ontario, Canada
Summary
🤩
Rockstar🎓
Top SchoolAnandh Venkateswaran is a Machine Learning Compiler Engineer with 7 years of experience building high-performance ML kernels and compiler toolchains for specialized accelerators. Currently at AWS working on the Neuron compiler for Trainium and Inferentia, he combines deep FPGA and RTL expertise with compiler- and runtime-level optimization to extract real-world performance. Previously he led SW/HW co-design and delivered Intel’s first production HBM FPGA platform, owning RTL micro-architecture, memory interconnects, and end-to-end verification. Anandh’s background spans startups to hyperscale tech—at Upverter he drove hardware product direction, and his early FPGA/PCB work powered video-encoding platforms—so he’s comfortable from schematic to silicon. He’s an active contributor to oneAPI samples (notably optimizing an FPGA-accelerated gzip), evidencing strong SYCL and FPGA-specific skills. Known for shipping timing-critical designs and debugging the most obscure failures, he blends hands-on engineering with technical leadership.
6 years of coding experience
9 years of employment as a software developer
Bachelor of Applied Science (B.A.Sc.) Honours Computer Engineering Co-op, Bachelor of Applied Science (B.A.Sc.) Honours Computer Engineering Co-op at University of Waterloo
Github Skills (5)
fpga10
gzip10
oneapi10
c-language10
cprogramming-language10
Programming languages (2)
Github contributions (5)
oneapi-src/oneAPI-samples
Sep 2020 - Jul 2022
Samples for Intel® oneAPI Toolkits
Role in this project:
Back-end Developer
Back-end DeveloperContributions:5 reviews, 18 commits, 19 PRs in 1 year 10 months
Contributions summary:Anandh primarily contributed to the "gzip" reference design within the oneAPI samples repository, focusing on performance optimization and bug fixes. Their work involved modifying C++ code related to FPGA acceleration, including adjustments to buffer allocations, kernel configurations, and compilation flags. The commits demonstrate a strong understanding of sycl and FPGA-specific extensions. The user also fixed compilation issues and improved the overall efficiency of the gzip implementation.
numbatoolkitsswrepoaplpower-management
anandhv/test
Jun 2019 - Jul 2019
Contributions:16 pushes in 1 month
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