Summary
Ananth Bhat is a hardware and verification engineer with nine years of experience building and validating FPGA and silicon designs across startups and major chip companies, currently a Member of Technical Staff at AMD in Bengaluru. He brings deep RTL and verification expertise (SystemVerilog, UVM) combined with practical experience in hardware acceleration, OpenCL parallel programming, and software automation from roles at SambaNova, NVXL, and AMD Pensando. Comfortable across the full chip flow, he has shipped projects on Intel and Xilinx FPGAs and used industry EDA tools including Quartus, Vivado, QuestaSim and Synopsys VC Formal. Colleagues rely on him for fast learning, decisive problem-solving in high-velocity teams, and bridging hardware-software boundaries. He pairs formal verification rigour with hands-on scripting in Python, C/C++, and Bash to speed bring-up and validation. Driven to take on challenging systems problems, he seeks opportunities to expand his impact across heterogeneous compute and silicon design.
9 years of coding experience
6 years of employment as a software developer
Engineer’s Degree, Electrical and Computer Engineering, Engineer’s Degree, Electrical and Computer Engineering at Portland State University
Bachelor’s Degree, Electronics Engineering, Bachelor’s Degree, Electronics Engineering at University of Mumbai
English, Hindi, Kannada