Ânderson Da Silva

Staff Digital Design Engineer at Qualcomm

Cork Metropolitan Area Ireland
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Summary

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Senior
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Top School
Ânderson Da Silva is a Staff Digital Design Engineer with 11 years of experience focused on high-performance CPU microarchitecture and secure SoC subsystems, currently leading Register Renaming and Retirement Unit work at Qualcomm in Cork. He has progressed from embedded hardware and SoC integration to leading safety-critical TME/Root-of-Trust projects, managing multi-site RTL teams and contributing to ISO26262 artifacts like DFMEA and FMEDA. Skilled in RTL design, high-speed AMBA interconnects, CPU-DPI modeling, and RISC-V integration, he blends low-level microarchitecture insight with practical firmware/debugging experience. His background includes designing accelerators for crypto and off-chip secure engines, and he has a master’s in Microelectronics Computer Engineering, reflecting strong academic grounding in IC design. Notably, he has repeatedly translated safety and security requirements into concrete RTL and verification solutions across large-scale, cross-site SoC programs.
code12 years of coding experience
job11 years of employment as a software developer
bookMaster's Degree in Microelectronics Computer Engineering, Master's Degree in Microelectronics Computer Engineering at Federal University of Rio Grande do Sul
bookBachelor's degree Electrical and Electronics Engineering, Bachelor's degree Electrical and Electronics Engineering at Unisinos
bookElectronic technician Electronic, Electronic technician Electronic at Fundaçao Escola Técnica Liberato Salzano Vieira da Cunha
languagesPortuguese, English, Spanish
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Github Skills (124)

verilog10
vhdl10
soc10
fpga10
risc-v10
router10
rocket10
axi410
ethernet10
chisel10
hdl10
agile9
python9
cpp9
rocket-chip9

Programming languages (15)

C++CMakefileScalaJupyter NotebookTypeScriptSystemVerilogSail

Github contributions (5)

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aignacio/nox

Jan 2024 - Jul 2025

RISC-V Nox core
Contributions:1 review, 3 PRs, 9 pushes in 1 year 6 months
risc-vrv32i
aignacio/riscv-formal

May 2019 - Jan 2022

RISC-V Formal Verification Framework
Contributions:10 commits, 11 pushes in 2 years 8 months
formal-verificationrisc-v
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