Andre Meyer
Co-Founder at Werktag GmbH
Bäretswil, Zurich, Switzerland
Summary
👤
Senior🎓
Top SchoolAndre Meyer is an electronic engineer and co-founder with nine years of professional experience designing embedded devices, sensor systems and imaging electronics, currently leading Werktag GmbH's hardware and FPGA efforts. He has deep domain expertise in safety-critical and medical-device electronics, having driven requirements, verification and lifecycle management for cloud-connected implantables and imaging systems. His background includes FPGA-heavy development for NMR spectroscopy at Bruker and earlier roles in medical and industrial imaging, reflecting a strong trajectory from hands-on hardware design to product-focused engineering leadership. Based in Bäretswil, Zurich and trained at ETH Zürich, he pairs rigorous academic grounding with practical craftsmanship—evidenced by a self-directed farmhouse renovation—bringing pragmatic problem solving to complex embedded systems.
9 years of coding experience
10 years of employment as a software developer
Master of Science (MSc), Electrical Engineering and Information Technology, Master of Science (MSc), Electrical Engineering and Information Technology at ETH Zürich
Stackoverflow
1reputation
0reached
0answers
0questions
Github Skills (35)
verilog9
fpga9
arduino8
ide8
vhdl8
eda8
lattice8
altera7
asic7
python7
xilinx7
data-acquisition7
command-line-tool6
cli6
vivado6
Programming languages (5)
Github contributions (5)
werktag/Adaino
Jun 2018 - Sep 2019
Adaino is an open source Analog Data Acquisition library for Arduino.
Contributions:1 release, 5 commits, 1 PR in 1 year 3 months
arduinodata-acquisition
andmeyee/andmeyee.github.io
Dec 2016 - Apr 2021
Contributions:15 pushes, 1 branch in 4 years 4 months
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