Summary
Andre Souto is a Staff ASIC designer with 11 years of experience building high-performance digital systems, currently leading micro-architecture, RTL design and verification for NVIDIA's BlueField RegEx accelerator. He blends deep FPGA/ASIC expertise (VHDL, Verilog, SystemVerilog, Specman e) with pragmatic tooling in Python to automate testing and accelerate delivery. His background spans telecoms, radar DSP and cloud FPGA ports, giving him a rare mix of algorithmic signal-processing insight and silicon-focused implementation skill. Known for introducing unit testing and SoC-like verification flows in FPGA teams, he emphasizes getting designs right first time through rigorous trade-off analysis and requirement management. Based in the UK, he pairs technical leadership with hands-on engineering and a persistent drive to build reliable, production-grade IP.
11 years of coding experience
12 years of employment as a software developer
Project Management, MBA, Project Management, MBA at Fundação Getulio Vargas
Electrical Engineering, Programmable logic, embedded systems, telecommunications, Electrical Engineering, Programmable logic, embedded systems, telecommunications at Federal University of Rio Grande do Sul
English, Portuguese