Andre Souto

Staff ASIC Designer - BlueField's RegEx Accelerator

Stony Stratford, England, United Kingdom
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Summary

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Senior
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Top School
Andre Souto is a Staff ASIC designer with 11 years of experience building high-performance digital systems, currently leading micro-architecture, RTL design and verification for NVIDIA's BlueField RegEx accelerator. He blends deep FPGA/ASIC expertise (VHDL, Verilog, SystemVerilog, Specman e) with pragmatic tooling in Python to automate testing and accelerate delivery. His background spans telecoms, radar DSP and cloud FPGA ports, giving him a rare mix of algorithmic signal-processing insight and silicon-focused implementation skill. Known for introducing unit testing and SoC-like verification flows in FPGA teams, he emphasizes getting designs right first time through rigorous trade-off analysis and requirement management. Based in the UK, he pairs technical leadership with hands-on engineering and a persistent drive to build reliable, production-grade IP.
code11 years of coding experience
job12 years of employment as a software developer
bookProject Management, MBA, Project Management, MBA at Fundação Getulio Vargas
bookElectrical Engineering, Programmable logic, embedded systems, telecommunications, Electrical Engineering, Programmable logic, embedded systems, telecommunications at Federal University of Rio Grande do Sul
languagesEnglish, Portuguese
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Stats
459reputation
66kreached
20answers
3questions
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Github Skills (79)

verilog10
quickfix10
python10
simulator10
statusline10
autocomplete10
ipython10
language-server-protocol10
coverage10
vim-plugin10
gcc10
vhdl10
vim10
lua10
altera10

Programming languages (13)

C++RustCValaTypeScriptSystemVerilogVHDLVerilog

Github contributions (5)

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suoto/fpga_cores

Oct 2014 - Jan 2023

Contributions:207 commits, 120 pushes, 7 branches in 8 years 4 months
suoto/grlib

Feb 2016 - Oct 2016

Contributions:4 releases, 4 commits, 2 pushes in 7 months
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