Andreas Käberlein is an experienced embedded systems and software engineer with eight years in industrial R&D, currently developing products at Siemens from Chemnitz. Trained as a Diplom-Ingenieur in microelectronics, he blends ASIC and FPGA design experience from academia with practical product development at Heitec and Siemens. His open-source contributions include implementing IRQ-driven SPI data transfer and FIFO-based frameworks for the NEORV32 RISC-V soft-core, reflecting deep familiarity with low-level firmware, VHDL and hardware-software integration. Multilingual and methodical, he thrives in international, cross-functional programs and often operates at the intersection of electronic design and scripting automation.
8 years of coding experience
5 years of employment as a software developer
Diplom-Ingenieur, Mikroelektronik, Diplom-Ingenieur, Mikroelektronik at Technische Universität Chemnitz
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Role in this project:
Embedded Systems Engineer / IoT Developer
Contributions:34 commits, 6 PRs, 2 pushes in 7 months
Contributions summary:Andreas primarily contributed to the development of an IRQ-driven SPI data transfer mechanism within the NEORV32 RISC-V soft-core CPU project. Their work involved introducing and refining functions for SPI interrupt service routines, and the implementation of a data transfer framework including the utilization of FIFO buffers. They also made modifications to the `neorv32_spi.c` and `neorv32_spi.h` files to integrate ISR based data flow and fix various related bugs.
Contributions:2 releases, 130 commits, 74 pushes in 7 months
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