Andreas Kurth
Silicon Lead at lowRISC CIC
Zurich, Zurich, Switzerland
Summary
🤩
Rockstar🎓
Top SchoolAndreas Kurth is a Silicon Architecture Lead with 9 years of experience designing, verifying, and architecting security-critical SoC IPs and top-level chips, currently leading silicon efforts at lowRISC from Zurich. He combines a strong computer-architecture foundation and full-stack hardware/software skills—spanning RISC-V core work, AXI infrastructure, and secure RoT subsystems like OpenTitan and OTBN—with hands-on RTL and verification contributions. As a technical lead and committee member at lowRISC he has driven Darjeeling RoT integration, IP sign-off, and cross-company collaboration processes that turned research-grade designs into production-ready silicon artifacts. His open-source track record includes practical fixes to CV32E40P instruction decoding, AXI and common SystemVerilog primitives, and security-hardening tests for Ibex, reflecting a pragmatic focus on robustness and verifiability. Notably, he pairs PhD-level research training from ETH Zurich with day-to-day engineering delivery, often surfacing subtle verification and side-channel issues before tape-out.
10 years of coding experience
8 years of employment as a software developer
Doctor of Science (Dr. sc.), Electrical Engineering and Information Technology, Doctor of Science (Dr. sc.), Electrical Engineering and Information Technology at ETH Zürich
Github Skills (29)
hardware-designs10
verilog10
systemverilog10
computer-architecture10
uvm10
it-security10
risc-v10
verification10
hardware-security-module10
security10
security-testing10
formal-verification10
sys10
rt10
embedded10
Programming languages (12)
Github contributions (5)
pulp-platform/axi
Nov 2018 - Aug 2022
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Role in this project:
Backend Developer & Hardware Engineer
Backend Developer & Hardware EngineerContributions:45 releases, 67 reviews, 1019 commits in 3 years 8 months
Contributions summary:Andreas made contributions focused on the hardware design aspects of the AXI IP modules. Their work involved modifying SystemVerilog code for AXI interfaces and modules like `axi_multicut` and `axi_id_remap`. They also introduced a new AXI ATOP filter and made modifications to the testbenches to incorporate the new features. Furthermore, they defined macros and updated the scripts to support design verification and testing of these IP modules.
systemverilogaxiaxi4axi4-litehardware
pulp-platform/common_cells
Jul 2018 - Feb 2020
Common SystemVerilog components
Role in this project:Software Engineer (SystemVerilog/RTL)
Software Engineer (SystemVerilog/RTL)Contributions:1 release, 23 reviews, 88 commits in 1 year 7 months
Contributions summary:Andreas primarily contributed to the development of SystemVerilog components, specifically focusing on stream-based communication primitives. Their work involved implementing and refining modules like stream registers, multiplexers, demultiplexers, arbiters, and filters. Furthermore, the user fixed issues and improved the FIFO design used within these stream components. These changes suggest a focus on low-level hardware design and efficient data transfer.
systemverilog
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