Andreas Olofsson
Chief Executive Officer at Zero ASIC
Cambridge, Massachusetts, United States
Summary
🤩
Rockstar🎓
Top SchoolAndreas Olofsson is a veteran semiconductor engineer and entrepreneur with 13+ years of leadership experience building silicon and tooling—currently CEO of Zero ASIC, focused on lowering the barrier to custom chips. He previously founded and led Adapteva, shipping Parallella single-board computers to thousands of customers and pioneering rapid tapeout techniques, and managed US microelectronics research portfolios at DARPA that advanced automated chip design and heterogeneous integration. Hands-on across circuit design, SoC architecture, and backend tooling, he contributes open-source Verilog libraries and improvements to the siliconcompiler ecosystem, combining practical EDA work with systems-level productization. Based in Cambridge, he blends academic rigor (MS/BS EE, BA Physics) with a track record of shipping high-volume devices and democratizing silicon through both commercial products and community projects.
12 years of coding experience
12 years of employment as a software developer
Greenwich High SchoolMS Electrical Engineering, MS Electrical Engineering at University of Pennsylvania
Swedish, Hebrew, English
Github Skills (14)
i2c10
hdl10
verilog10
embedded10
c-programming10
sys10
python10
vhdl10
image-processing9
pg9
rtl-design9
fpga9
documentation8
build-system5
Programming languages (10)
Github contributions (5)
siliconcompiler/siliconcompiler
Dec 2020 - Jan 2023
Modular hardware build system
Role in this project:
Back-end Developer
Back-end DeveloperContributions:416 reviews, 3037 commits, 378 PRs in 2 years 1 month
Contributions summary:Andreas's commits primarily involve adding a layout picture, which is added to the user guide, tests and examples, and shortening the show_file to show() in the core.py file. They also updated a test for inferring die size, and flushed out the introduction chapter of the user guide, including adding example code and diagrams. The user demonstrates skills in software architecture, including integrating code with design tools by using the silicon compiler infrastructure, contributing to the improvement of the modular hardware build system.
vhdledasynthesislatticehardware
aolofsson/oh
Nov 2014 - Oct 2022
Verilog library for ASIC and FPGA designers
Role in this project:Embedded Systems Engineer
Embedded Systems EngineerContributions:1 review, 1446 commits, 54 PRs in 8 years
Contributions summary:Andreas's contributions primarily involve modifying and implementing Verilog code within the context of a Verilog library designed for ASIC and FPGA designers. Their work focused on enhancing the functionality of the library, specifically related to the design and implementation of synchronous and asynchronous FIFO (First-In, First-Out) memory structures. The user's commits involve integrating the memory management unit to address existing bugs.
designersasicvivadoyosyseda
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