Andres Garcia
Senior CPU Architect at Google
London, England, United Kingdom
Summary
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Rockstar🎓
Top SchoolAndres Garcia is a Senior CPU Architect based in London with a decade of experience designing and validating processors for companies like Google, Codasip and Arm. His work spans ISA and RTL design, verification, performance modelling and the CHERI security extension for RISC-V, and he contributed substantial portions of that specification. With a PhD focused on hardware garbage collection and real-time embedded systems, he blends deep academic research with practical engineering—having helped design the A730 RISC-V application processors. He also has a background in applied security from maintaining Mbed TLS and publishes technical writing on embedded systems and architecture at sourcecodeartisan.com.
10 years of coding experience
7 years of employment as a software developer
Doctor of Philosophy - PhD Computer Science, Doctor of Philosophy - PhD Computer Science at University of Bristol
English, Spanish, French
Stackoverflow
391reputation
99kreached
8answers
10questions
Github Skills (71)
mbed10
python10
internet10
micropython10
arm10
embedded10
operating-system10
portable10
crypto10
linux10
api10
readable10
kernel10
memory-safety10
ssl10
Programming languages (5)
Github contributions (5)
andresag01/riscv-cheri
Jan 2024 - Feb 2025
This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
Contributions:2 PRs, 64 pushes, 53 branches in 1 year 1 month
andresag01/mbed-os-example-tls
Sep 2016 - Dec 2018
mbed TLS Sample application
Contributions:42 pushes, 31 branches in 2 years 2 months
mbedtlssslsample-application
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