Andrew Lenharth
Principal Engineer at SiFive
Austin, Texas, United States
Summary
🤩
Rockstar🎓
Top SchoolAndrew Lenharth is a Principal Engineer in Austin with 12+ years turning compiler and language research into production-grade hardware tooling, currently leading a 25-person team at SiFive that builds novel hardware languages, compilers, and flows. A technical lead on the CIRCT LLVM incubator and contributor to Chisel, he specializes in bringing FPGA and RTL design into modern developer toolchains through compiler-driven approaches to verification, simulation, and build/test automation. His background spans academia and industry—PhD-trained research on irregular and parallel algorithms, top-rated teaching at UT Austin, and FPGA language work at Microsoft—giving him a rare mix of deep theory and pragmatic engineering. Notably, he’s integrated CIRCT intrinsics into Chisel and implemented RTL comparison lowering and Verilog emission, demonstrating hands-on impact on widely used open-source hardware projects.
12 years of coding experience
19 years of employment as a software developer
Bachelor of Engineering (BE) Computer Engineering, Bachelor of Engineering (BE) Computer Engineering at University of WashingtonDoctor of Philosophy (PhD) Computer Science, Doctor of Philosophy (PhD) Computer Science at University of Illinois Urbana-Champaign
Stackoverflow
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Github Skills (13)
rt10
circuit10
verilog10
cil10
firrtl10
cct10
scala10
chisel9
low-level-programming8
compiler-design8
hardware-designs8
generator7
chip87
Programming languages (10)
Github contributions (5)
llvm/circt
Oct 2020 - Jan 2023
Circuit IR Compilers and Tools
Role in this project:
Back-end Developer
Back-end DeveloperContributions:17 releases, 1510 reviews, 802 commits in 2 years 3 months
Contributions summary:Andrew made contributions focused on adding comparison operators to the RTL dialect within the circuit IR compilers and tools repository. This involved implementing functionality for the FIRRTL to RTL lowering and RTL to Verilog emission for comparison operators. The user's commits also included modifications to test files, ensuring the proper testing and verification of the newly added features, alongside fixes. Furthermore, the user contributed code to the emit Verilog and include/circt/Dialect/RTL/Visitors.h, ensuring that the language supported features for comparing hardware designs.
compilercirctllvmmlir
chipsalliance/chisel
Jan 2023 - Jan 2023
Chisel: A Modern Hardware Design Language
Role in this project:Backend Developer
Backend DeveloperContributions:40 reviews, 1 commit, 8 PRs in 1 day
Contributions summary:Andrew primarily worked on adding and integrating CIRCT intrinsic wrappers within the Chisel hardware design language. Their contributions include the creation of modules for `SizeOf`, `PlusArgsValue`, `PlusArgsTest`, and `IsX` intrinsics, which enhance Chisel's interaction with underlying hardware tools. They also modified existing files to incorporate these new intrinsic modules, along with testing and documentation. Their work included extending the core library to facilitate better interoperability with CIRCT and hardware generation.
chiselhardware-designschisel3scalafirrtl
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