Andrew Moch
Chief HW Engineer at Emerson
Austin, Texas, United States
Summary
🤩
Rockstar🎓
Top SchoolAndrew Moch is a seasoned hardware engineer and technical leader with roughly six years of documented experience and longstanding roles as Chief HW Engineer at Emerson and Principal Architect at National Instruments, specializing in ASIC and FPGA design and verification. Based in Austin, he brings deep hands-on expertise in embedded systems, FPGA toolchain integration, and AXI/10 GbE interfaces, evidenced by contributions to the well-known EttusResearch UHD repository where he added ModelSim simulation support and advanced AXI features. He pairs rigorous academic grounding—a 3.99 BS in Computer Engineering from Texas A&M—with practical experience streamlining simulation, linting, and testbench workflows to improve hardware verification cycles. Known for bridging low-level FPGA development and system-level architecture, he focuses on making complex hardware toolchains more maintainable and automated. Colleagues can expect a pragmatic engineer who moves fluently between scripting, makefile orchestration, and high-performance digital design.
6 years of coding experience
Bachelor of Science (BS), Computer Engineering (EE Emphasis), 3.99, Bachelor of Science (BS), Computer Engineering (EE Emphasis), 3.99 at Texas A&M University
Github Skills (8)
fpga10
verilog10
systemverilog10
makefile10
axi410
sdl8
uhd7
driver6
Programming languages (1)
Github contributions (1)
EttusResearch/uhd
Mar 2020 - Aug 2021
The USRP™ Hardware Driver Repository
Role in this project:
Back-end & Embedded Systems Engineer
Back-end & Embedded Systems EngineerContributions:26 commits, 7 pushes, 1 branch in 1 year 5 months
Contributions summary:Andrew primarily focused on adding support for ModelSim simulation, including targets for linting and running simulations natively. They modified makefiles and scripts to integrate ModelSim, manage simulation arguments, and compile files. They also fixed errors found during linting and updated various testbenches and modules related to FPGA development within the repository. Furthermore, they added features to the AXI4-Lite and AXI4 interfaces and also introduced new functionalities to the 10 GbE cut-through mode.
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