Andrew Raseley
Principal Engineer at BRIDG
Allentown, Pennsylvania, United States
Summary
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Senior🎓
Top SchoolAndrew Raseley is a Principal Engineer with over a decade of hands-on experience designing and commercializing systems-level solutions for high-data-rate optical communications and advanced semiconductor packaging. He has led architecture, firmware, test automation, NPI, and manufacturing-yield improvements across 100G–800G+ modules and heterogeneous PIC-based subsystems, blending hardware, firmware, and systems engineering. At BRIDG he now helps on-shore advanced interposer and packaging technologies while previously driving firmware and automated test systems that bridged lab prototypes to high-yield production. Colleagues rely on him to translate complex optical and packaging constraints into practical, MSA-compliant control interfaces and manufacturable assemblies. He brings a pragmatic, cross-disciplinary approach—equally comfortable debugging DSP/optical metrics as scripting factory automation—and enjoys collaborating across organizations to push emerging packaging and photonics technology forward. Based in Allentown, PA, he pairs a Lehigh Computer Engineering foundation with a track record of improving yields and enabling customers through robust product engineering.
10 years of coding experience
10 years of employment as a software developer
Pleasant Valley High SchoolBachelor of Science (B.S.), Computer Engineering, Bachelor of Science (B.S.), Computer Engineering at Lehigh University
Github Skills (4)
joystick10
keyboard9
aviation7
windows6
Programming languages (1)
Github contributions (5)
AR-AR-AR/CLN
Aug 2025 - Sep 2025
Contributions:3405 pushes, 1 branch in 24 days
AR-AR-AR/IF_Utility
Dec 2015 - Jan 2016
Contributions:1 release, 9 pushes, 1 branch in 7 days
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