Andrew Tran
Distinguished MTS at Astera Labs
San Francisco Bay Area United States
Summary
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Senior🎓
Top SchoolAndrew Tran is a Distinguished MTS based in the San Francisco Bay Area with eight years focused on high-speed ASIC/FPGA architecture, reconfigurable SoCs, and AI accelerators for data-center connectivity and low-latency memory systems. He has a strong track record of bringing complex silicon from concept to tapeout across process nodes (65nm to 16nm), including multiple SDN and AI chips and a 28nm CMOS AI processor at a founding startup. Prior roles span leadership and hands-on engineering—CTO of an ML model compiler/ASIC/FPGA startup and senior ASIC design at Cavium—bridging system-level architecture with RTL and verification. His Ph.D. work on on-chip networks and ongoing focus on PCIe/CXL, DDR, and network switch interconnects give him deep domain expertise in both hardware design and system integration. An active GitHub presence documents his continued engineering focus on ASIC and embedded system projects, reflecting a blend of research rigor and product-driven execution.
8 years of coding experience
9 years of employment as a software developer
Doctor of Philosophy (Ph.D.), Electrical Engineering, Doctor of Philosophy (Ph.D.), Electrical Engineering at University of California, DavisBachelor of Science (B.S.), Electronics Engineering, Bachelor of Science (B.S.), Electronics Engineering at Posts and Telecommunications Institue of Technology, HCMC, VietnamHigh School, Mathematics, High School, Mathematics at VNU-HCM High School for the GiftedSoftware Engineering, Software Engineering at University of Technology, HCMC, VietnamGithub contributions (5)
anhtranproj/vlib
Nov 2019 - Jun 2020
Contributions:26 commits, 35 pushes, 1 branch in 7 months
anhtranproj/tensorflow_util
Oct 2019 - Jan 2020
Contributions:8 pushes in 2 months
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