Andrew Waterman
Privileged Architecture ISA Committee Vice Chair at SiFive
Berkeley, California, United States
Summary
🤩
Rockstar🎓
Top School
Top expert inDigital Hardware Design and Verification
Andrew Waterman is a RISC-V architect and co-founder of SiFive with 14 years of systems and hardware-software co-design experience, currently serving as Privileged Architecture ISA Committee Vice Chair at RISC-V International and Chief Engineer at SiFive. He combines deep academic training (Ph.D., UC Berkeley) with practical impact across open-source toolchains and hardware compilers—contributing to FIRRTL, Chisel, Spike, riscv-gnu-toolchain and the RISC-V ISA manual. His work spans low-level simulator and toolchain engineering, privileged ISA and virtual memory design, and compiler/codegen optimizations that improve generated RTL and Verilog quality. Notably, he helped eliminate dependencies in Spike with a custom disassembler and added key privileged/SV39–SV64 encodings and tests, reflecting both specification authorship and hands-on implementation. Based in Berkeley, he uniquely bridges standards leadership and day-to-day engineering, driving features from specification through simulator, compiler, and silicon.
14 years of coding experience
4 years of employment as a software developer
Doctor of Philosophy (Ph.D.), Computer Science, Doctor of Philosophy (Ph.D.), Computer Science at University of California, BerkeleyBSE, Electrical and Computer Engineering, BSE, Electrical and Computer Engineering at Duke University
Github Skills (61)
hardware-designs10
simulation10
verilog10
assembly10
c-language10
system-programming10
simulator10
architecture10
computer-architecture10
simulations10
risc-v10
memory-management10
verification10
bash10
firrtl10
Programming languages (15)
Github contributions (5)
riscv/riscv-opcodes
Mar 2012 - Jan 2023
RISC-V Opcodes
Role in this project:
Back-end Developer / Systems Architect
Back-end Developer / Systems ArchitectContributions:158 reviews, 146 commits, 196 PRs in 10 years 11 months
Contributions summary:Andrew primarily contributed to the `riscv-opcodes` repository by modifying the `encoding.h` and `inst.v` files. Their work focused on updating instruction encodings, including adding new privileged ISA features and virtual memory support (SV39, SV48, SV57, and SV64). These changes involved modifying existing CSR registers and adding new ones, and also renaming and modifying existing fields and constants, improving the overall structure and functionality of the RISC-V opcode definitions. These modifications appear aimed at supporting new features and standardizing the instruction set.
risc-vriscopcodesfpga
riscv-software-src/riscv-tools
Nov 2011 - Mar 2019
RISC-V Tools (ISA Simulator and Tests)
Role in this project:Automation Engineer / Build & Release Engineer
Automation Engineer / Build & Release EngineerContributions:1 release, 100 commits, 41 PRs in 7 years 5 months
Contributions summary:Andrew primarily contributed to the build system of the RISC-V tools. They modified build scripts (`build.sh`, `build-rv32ima.sh`, `build-spike-pk.sh`, `build-spike-only.sh`) to update toolchain configurations and dependencies, integrating new components and resolving conflicts. The changes include updating compiler versions, modifying build parameters, and merging code from different branches.
risc-visariscvsimulatorrisc
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