Andrew Wygle
Principal Software Engineer at Hashflow
Spokane, Washington, United States
Summary
🤩
Rockstar🎓
Top SchoolAndrew Wygle is a Principal Software Engineer with over a decade of experience designing embedded and distributed systems, blending deep firmware expertise with high-performance analog and high-speed digital PCB design. He holds a B.S. in EECS from UC Berkeley and has led engineering efforts across startups and established firms, most recently at Hashflow after senior roles at MobileCoin and Data I/O. Andrew is an active open-source contributor to notable hardware toolchains—adding LM4K support to Project IceStorm, improving Amaranth's AsyncFIFO semantics, and enhancing Glasgow's low-level JTAG/I2C features—demonstrating a knack for reverse engineering and reliable hardware-software integration. He brings systems-level thinking to problems spanning FPGA toolchains, build tooling (FuseSoC), and embedded IoT devices, often tackling subtle reset/CDC and timing issues that others miss. Based in Spokane, Washington, he pairs hands-on technical delivery with architectural judgment and a history of founding a hardware startup, reflecting an engineer comfortable from PCB layout to production firmware.
10 years of coding experience
13 years of employment as a software developer
B.S. Electrical Engineering and Computer Science, B.S. Electrical Engineering and Computer Science at University of California, BerkeleyNewbury Park High School
Spanish
Github Skills (33)
debugging10
verilog10
debug10
python10
hardware10
pg10
digital-logic10
vhdl10
i2c10
digital-design10
sys10
hdl10
fpga10
embedded10
package-manager10
Programming languages (10)
Github contributions (5)
amaranth-lang/amaranth
Mar 2020 - Nov 2020
A modern hardware definition language and toolchain based on Python
Role in this project:
Software Engineer
Software EngineerContributions:5 reviews, 9 commits, 18 PRs in 8 months
Contributions summary:Andrew primarily focused on enhancing the `amaranth-lang/amaranth` project, a hardware definition language and toolchain. Their contributions involved improving the `AsyncFIFO` module, addressing reset handling to maintain FIFO and CDC invariants. Further work included careful type checking of the `convert` function's `ports` argument, and adding the `r_rst` output to `AsyncFIFO{,Buffered}`. Additionally, the user migrated the `Record` class from `UserValue` to `ValueCastable` and proxied operators correctly, including restoring the `shape()` method.
verilogasicpythonhdlyosys
olofk/fusesoc
Nov 2017 - Mar 2018
Package manager and build abstraction tool for FPGA/ASIC development
Role in this project:Back-end Developer
Back-end DeveloperContributions:19 commits, 8 PRs, 10 comments in 3 months
Contributions summary:Andrew primarily focused on refactoring and improving the `fusesoc` project, a package manager and build tool for FPGA/ASIC development. They de-single the `CoreManager` and `Config` classes, indicating a focus on improving the architecture and maintainability of the tool. Furthermore, the user introduced features for better Windows support and library management, demonstrating a commitment to enhancing the tool's usability and expanding its functionality.
asicpythonvhdledapackage-manager
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