Yosys Open SYnthesis Suite
Role in this project:
Back-end Developer Contributions:170 commits, 36 PRs, 20 comments in 3 years 7 months
Contributions summary:Andrew made significant contributions to the Yosys Open SYnthesis Suite, primarily focused on enhancing the SAT solver functionality. Their work included the addition of a new argument "-dump_fail_to_vcd" to the SAT solver, and the implementation of the Verilog System Task, $finish(). The user also implemented, improved and expanded upon system tasks like $display and the GreenPak4 counter functions to support user logic and added more simulation models.
synthesispythonsuiteyosys
Contributions:21 commits, 2 PRs, 18 pushes in 2 years 4 months
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