Andrey Ayupov
Summary
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SeniorAndrey Ayupov is a Silicon Engineer with nine years of focused experience in rapid hardware-accelerator design and a two-decade research pedigree in high-level synthesis and ML accelerator architecture. Currently leading the TPU (Tensor SoC) architecture team at Google, he bridges system-level architecture exploration with hands-on microarchitecture and Chisel-based hardware design. Previously at Intel he pioneered high-level synthesis methodologies for ASIC and FPGA targets, combining SystemC modeling, performance modeling, and agile hardware design practices. He holds a PhD in Computer Science (EDA) from MIPT and is known for translating research insights into practical accelerator prototypes and synthesis flows. Andrey’s work uniquely spans academia-grade EDA rigor and production-focused SoC delivery, making him adept at collapsing design cycles for emerging ML workloads. Based in the San Francisco Bay Area, he brings both deep technical craft and leadership in next-generation accelerator architecture.
9 years of coding experience
Github Skills (9)
intermediate9
hardware-designs9
verilog9
chisel8
scala8
hardware8
transformation8
firrtl7
compiler5
Programming languages (2)
Github contributions (5)
aayupov/firrtl
Jul 2017 - Aug 2017
Contributions:7 pushes, 2 branches in 9 days
representationrtlflexibleintermediateintermediate-representation
intel/rapid-design-methods-for-developing-hardware-accelerators
May 2017 - Jun 2018
Contributions:20 commits, 1 PR, 5 pushes in 1 year 1 month
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