Andy Traber
Staff Site Reliability Engineer at Google
Zurich, Zurich, Switzerland
Summary
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Rockstar🎓
Top SchoolAndy Traber is a Staff Site Reliability Engineer based in Zurich with 13 years of experience building reliable, scalable systems and deep expertise bridging hardware and software. At Google he progressed from SRE to staff-level responsibilities, applying operational rigor to large distributed services while drawing on prior hands-on SoC and RISC-V CPU design experience. His open-source contributions to prominent RISC-V cores (CV32E40P and CVA6) show a rare combination of hardware description, verification, and debugger/debug-unit design—skills that inform his pragmatic approach to observability and low-level troubleshooting. Trained at ETH Zurich in electrical engineering, he brings research-grade attention to detail from ultra-low-power SoC work and production-grade engineering practiced at a hyperscaler. Notably, he has experience adapting complex hardware code for modern toolchains (Verilator) and modularizing debug functionality, reflecting a taste for improving toolchain compatibility and code hygiene.
13 years of coding experience
7 years of employment as a software developer
Master of Science (MSc), Elektrotechnik und Informationstechnologie, Master of Science (MSc), Elektrotechnik und Informationstechnologie at Eidgenössische Technische Hochschule Zürich
German, English, French
Stackoverflow
11reputation
1kreached
1answer
0questions
Github Skills (14)
vhdl10
hdl10
cpu10
risc-v10
verilator10
debug10
debugging10
systemverilog10
asic9
fpga9
cpu-architecture9
design-patterns6
php6
dom6
Programming languages (8)
Github contributions (5)
openhwgroup/cv32e40p
Aug 2015 - May 2016
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Role in this project:
Back-end Developer
Back-end DeveloperContributions:202 commits, 3 pushes, 1 branch in 9 months
Contributions summary:Andy focused on implementing and refining debug features for the RISC-V CPU, specifically within the context of the CV32E40P in-order RISC-V RV32IMFCXpulp CPU. They made significant contributions to the debug support, including software breakpoints, and setting a new PC from the debugger. They also refactored the code by moving debug functionality and the program counter to a dedicated debug unit to improve the modularity of the code.
risc-vcpupulpuvmriscv
openhwgroup/cva6
Oct 2017 - Nov 2017
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Role in this project:Embedded Systems Engineer
Embedded Systems EngineerContributions:5 commits in 18 days
Contributions summary:Andy primarily contributed to the hardware description and verification aspects of the CVA6 RISC-V core. Their work involved modifying SystemVerilog code, renaming types to avoid parser conflicts, and adapting the code to be compatible with the Verilator tool. This included changes in `ariane.sv`, `mmu.sv`, and related package files. Furthermore, the user added timeunits to the packages and removed superfluous semicolons, indicating a focus on code quality and toolchain compatibility within a hardware description environment.
cpurisc-vasicbootingariane
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