Andy Yang

Cursor Campus Lead at MIT Political Science

Boston, Massachusetts, United States
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Summary

👤
Senior
🎓
Top School
Andy Yang is a software engineer and MIT CS/AI and Finance student with a decade of hands-on experience across machine learning research, AI policy, and software engineering internships at institutions like Google and MIT. He blends research-grade ML work—designing deep learning systems for PDE simulation and optimal transport on manifolds—with real-world product contributions, including documentation and bug fixes to the widely used Yosys open synthesis suite. Comfortable at the intersection of technology, policy, and entrepreneurship, Andy has translated technical insight into policy briefs for AI governance and expanded developer communities as a campus lead for Cursor. His leadership roots trace to civic programs where he served as State Speaker and Attorney General at Palmetto Boys State, reflecting a rare combination of technical depth, public-facing communication, and civic engagement.
code10 years of coding experience
job3 years of employment as a software developer
bookBS Computer Science and Finance, BS Computer Science and Finance at Massachusetts Institute of Technology
bookSTEM Scholar with Honors, STEM Scholar with Honors at Dutch Fork High School
languagesChinese, English, Spanish
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Github Skills (8)

synthesis10
open-source10
yosys10
c-language10
cprogramming-language10
documentation10
verilog7
python4

Programming languages (10)

TypeScriptC++ShellCTeXVerilogHaskellTcl

Github contributions (5)

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YosysHQ/yosys

Sep 2018 - Jun 2019

Yosys Open SYnthesis Suite
Role in this project:
userTechnical Writer & Bug Fixer
Contributions:6 commits, 4 PRs, 2 comments in 9 months
Contributions summary:Andy primarily contributed to fixing typos and improving the clarity of help messages within the Yosys Open SYnthesis Suite. Their work focused on correcting documentation and minor code errors related to various commands, including `sim`, `verilog_write`, and `ice40_unlut`. They also addressed an issue with pyosys commands, ensuring correct return types. These contributions enhanced the user experience and documentation quality of the software.
synthesispythonsuiteyosys
csail-csg/riscy

Jul 2016 - May 2017

Contributions:2 releases, 207 commits, 4 PRs in 10 months
risc-vriscvriscprocessors
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