Anil Sharma
Asic Verification Technical Lead
Bengaluru, Karnataka, United States
Summary
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Rockstar🎓
Top SchoolAnil Sharma is an ASIC verification technical lead with two decades of experience at Intel, specializing in SystemVerilog OVM and both IP and SoC verification. He brings deep protocol expertise in USB, PCI, Display, PIPE and six years focused on high-speed I/O (HSIO) design and validation. At Intel he has led verification efforts across complex subsystems, marrying rigorous verification methodology with pragmatic engineering to close silicon bring-up gaps. Anil also contributes to open-source verification tooling—improving the RISC-V instruction generation flow in the widely used riscv-dv project—demonstrating a hands-on approach to testbench and generator robustness. Trained in Electrical and Electronics Engineering at BITS Pilani, he blends strong academic foundations with long-term industrial practice. Known for spotting subtle test-generation bugs, he strengthens verification pipelines that directly improve processor and IP reliability.
8 years of coding experience
BITS Pilani, Birla Institute of Technology and Science
Stackoverflow
21reputation
11kreached
2answers
1question
Github Skills (9)
risc-v10
python10
testing10
systemverilog9
code-generation9
verilog9
scripting8
hdl6
sorting6
Programming languages (5)
Github contributions (5)
chipsalliance/riscv-dv
Apr 2020 - Jun 2022
Random instruction generator for RISC-V processor verification
Role in this project:
Software Engineer
Software EngineerContributions:43 reviews, 97 commits, 49 PRs in 2 years 1 month
Contributions summary:Anil contributed to the RISC-V instruction generator for processor verification by fixing a typo in the `riscv_instr_test_lib.sv` file and adding and updating `pygen_src` files, including `riscv_instr.py`, `riscv_instr_stream.py` and `rv32i_instr.py`. These changes suggest a focus on improving the code generation process and addressing errors within the test library. The user's work likely improved the accuracy and functionality of the RISC-V instruction generation.
risc-v
saurabhsingh-pvips/riscv-dv
May 2020 - Jun 2022
SV/UVM based instruction generator for RISC-V processor verification
Contributions:23 PRs, 391 pushes, 103 branches in 2 years
risc-vriscinstructionverificationuvm
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