Anmol Saxena
Bengaluru, Karnataka, India
Summary
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Top SchoolAnmol Saxena is a Senior Design Engineer at Qualcomm in Bengaluru with four years of hands-on experience in RTL and Network-on-Chip (NoC) architecture and ASIC design. He progressed from an entry design engineer role at Cientra to client-facing Qualcomm positions starting in 2022, and transitioned to a direct Qualcomm senior role in 2026, demonstrating rapid technical growth and strong cross-organizational collaboration. Holding an M.Tech in ICT with a VLSI and Embedded Systems specialization, he blends academic rigor with practical silicon-focused engineering. Known for deep RTL expertise, he contributes to complex on-chip interconnect and digital hardware solutions while continually expanding system-level NoC knowledge. Anmol’s background as a teaching assistant and steady internal promotions hint at both mentorship ability and consistent delivery under evolving project scopes.
4 years of coding experience
4 years of employment as a software developer
Bachelor of Technology - B.Tech, Electrical and Electronics Engineering, Bachelor of Technology - B.Tech, Electrical and Electronics Engineering at Vellore Institute of TechnologyMaster of Technology - M.Tech, Information and Communication Technology with specialization in VLSI and Embedded Systems, Master of Technology - M.Tech, Information and Communication Technology with specialization in VLSI and Embedded Systems at Dhirubhai Ambani Institute of Information and Communication TechnologyGithub contributions (5)
Anmol-wq/Clock_Generator
Feb 2022 - Feb 2022
Contributions:22 commits, 20 pushes, 1 branch in 1 day
Anmol-wq/VSD-Synopsys-DC-Synthesis-and-STA
Sep 2021 - Sep 2021
Contributions:5 commits, 4 pushes, 1 branch in 6 days
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